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RISC-V
来自开放百科 - 灰狐
（版本间的差异）
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==项目== | ==项目== | ||
| + | 涉及 [[proof assistant]]、软硬件规范、形式化语言、定理验证等领域 | ||
| + | [[文件:Formal-Verification.png]] | ||
| + | [[文件:Corespec.png|right]] | ||
| + | |||
| + | *[https://deepspec.org The Science of Deep Specification] [https://deepspec.org/entry/Project/Haskell+CoreSpec Haskell CoreSpec] [https://riscv.org/wp-content/uploads/2017/12/Wed-1454-RISCV-AdamChlipala.pdf Strong Formal Verification for RISC-V] | ||
| + | *[https://wiki.haskell.org/Specification_and_proof Specification and proof] [https://programatica.cs.pdx.edu/P/diatchi.pdf A Formal Specification of the Haskell 98 Module System] | ||
| + | *[https://cnrv.io/resource RISC-V资源列表] | ||
| + | *[https://github.com/GaloisInc/grift GRIFT] A richly-typed, deeply-embedded RISC-V semantics written in Haskell | ||
| + | *[https://github.com/standardsemiconductor/lion Lion] Where Lions Roam: RISC-V on the VELDT | ||
| + | *[https://github.com/mit-plv/riscv-semantics riscv-semantics] A formal semantics of the [[RISC]]-V ISA in Haskell | ||
| + | *[https://gergo.erdi.hu/retroclash/ Retrocomputing with Clash: Haskell for FPGA Hardware Design] | ||
| + | *[https://forsyde.github.io ForSyDe] A Methodology for Formal System Design（形式化系统设计的方法论） | ||
==处理器== | ==处理器== | ||
2022年5月17日 (二) 02:21的版本
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您可以在Wikipedia上了解到此条目的英文信息 RISC-V Thanks, Wikipedia. |
RISC-V
目录 |
简介
RISC-V 是一个基于精简指令集（RISC）原则的开源指令集架构（ISA），开源硬件运动的核心项目。
基金会
设计
项目
涉及 proof assistant、软硬件规范、形式化语言、定理验证等领域
- The Science of Deep Specification Haskell CoreSpec Strong Formal Verification for RISC-V
- Specification and proof A Formal Specification of the Haskell 98 Module System
- RISC-V资源列表
- GRIFT A richly-typed, deeply-embedded RISC-V semantics written in Haskell
- Lion Where Lions Roam: RISC-V on the VELDT
- riscv-semantics A formal semantics of the RISC-V ISA in Haskell
- Retrocomputing with Clash: Haskell for FPGA Hardware Design
- ForSyDe A Methodology for Formal System Design（形式化系统设计的方法论）
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